The aim of this paper is to present a solution to the optimum radix
problem in multiple-valued logic systems.
This paper solves for the optimum radix problem based on the pinout-problem
and the multiplexing-time problem of digital components. The paper shows that
the quaternary digital system is an optimum solution. Unlike other solutions provided in current literature, the
method of this paper solved for the optimum solution as an exact integer number
equal to four. The solution does
not round off its result to the closest integer as in the case of some current
solutions in the literature
Keywords: Multiple-Valued Logic Systems, Optimum Radix, Quaternary.
Optimum Radix In
Many characteristics of digital systems are reflected due to their
radices such as the data length, circuit complexity, interconnection complexity,
the total pins of a digital component, the address bus width, the data bus
width, the number of representations, power consumption, the speed of arithmetic
etc. Some of these characteristics are enhanced as we increase
the radix of a system and some are not. For example, if the data and address buses lines are decreased,
the total number of pins is reduced, interconnection complexity is reduced,
etc. However, these
characteristics are not linearly enhanced all the time and for all types of
components as we increase the radix. Some
components may best operated at radix 16, others may be at radix four, and
others may be at radix two. Due to
the various changes to these characteristics, the solution to the optimum radix
should be an important issue. Thus,
what is the optimum radix relative to given constraints?
Hurst in  showed that the optimum radix is equal to e=2.718.
By rounding this number to three, he suggested that three-valued systems
are the most economical. In his analysis he assumed that circuit complexity is
linearly proportional to the system radix. According to George Abraham in 
this assumption has to be verified. Also,
according to Butler in , practical cases do not support the linearity
assumption. Also, based on their analysis on deriving an empirical relation
between cost and radix, Allen and Givone in  showed that the optimum system
is strictly greater than not equal to e=2.71 but they did not solve for the
current study of this paper presents a different approach to the optimum
problem. In this paper, we analyzed the optimum problem based on the pinout-problem
and the multiplexing-time problem. We assumed the current digital system radix is B and the new
digital system that will optimize the pinout-problem and the multiplexing-time
problem relative to the B-radix system is the z-radix system. By these
analysis we derived an overall performance function of digital components that
measures the system performance using the gain in pins-cut and the gain in
multiplexing-time. This performance
function depends on the system to be optimized and on the optimizing system. We
found the first derivative of this performance function and solved for the
optimum system to be Zoptimum=B2.
By setting B=2 which corresponds to the binary system and substituting in
the optimum equation. (Zoptimum=22=4) we found that the
optimum system that will optimize the binary system is the quaternary system.
The following analysis of finding the optimum system considers the pinout-problem
and the multiplexing-time problem in digital circuits. First, we will
analyze with respect to the pinout-problem and then with respect to the
Assume the current digital system radix is B and the new digital
system that will optimize the pinout-problem and the multiplexing-time problem
relative to the B-radix system is the z-radix system.
Let the number of pins of a data bus in a digital component in the z-radix
system be denoted by Nz and in the B-radix
system by NB and the difference between the
two numbers denoted by Ncut where Ncut=NB-Nz.
In order to compare the two components in both systems we define the gain in
pins-cut between the two systems as Gpins-cut=Ncut/NB.
From the preceding equation we have Gpins-cut=(NB-Nz)/NB.
Since the component in the B-radix system has a bus with NB
lines, then this bus must have an equivalent bus in the z-radix system with Nz
lines so that both buses handle the same amount of data. In order to satisfy
this equivalence condition, we have to have ZNz=BNB.
By taking the natural log of both sides we obtain NzLn(z)=NBLn(B).
By solving for the ratio Nz/NB
we obtain Nz/NB=Ln(B)/Ln(z)
and substituting in the Gpins-cut we obtain
Assume we have the same set of data stored in similar components in both
systems. Assume we would like to transfer data across a telephone line in
each component serially and evaluate the overall multiplexing-time needed to
transfer data. The data size will be measured by the number of digits in
each system that represent data itself. Assume data size in the B-radix is given
by DB B-digits (ex. 21 bits)
and the data size in the z-radix system is given by DZ Z-digits
(ex. 7 octal-digit). Each digit in either system is transferred out of the
component by one-clock cycle with a period of T0. The
total multiplexing-time for the data in the B-system is given by TB=DBT0
and for the z-system it is given by Tz=DzT0.
To compare both times we have to unify the unit of measurements in both systems.
A Z-Digit in the Z-system is equivalent to Ln(z)/Ln(B) digits in B-system.
That is Z-digit=[Ln(z)/Ln(B)]
B-digits. We also require that the data in both systems to be
equivalent. That is DZ ºDB, but DZ is measured
in Z-digits and DB is measured in B-digits. Thus Data=DZ
=DB Ln(B)/Ln(Z) in units of Z-digits. The time
needed to transfer a z-digit or a B-digit is equal to the time of one clock
cycle. Now we define the gain in transmission-time as Gtime=TZ/TB=DZT0/DBT0=
Ln(B)/Ln(Z)*1/DB. Finally we get Gtime=Ln(B)/Ln(z).
gain in multiplexing-time "Gtime" dose not imply by any
means a linear speed-up with higher radices because it measures the relative
multiplexing-time of data in the z-radix system to the multiplexing-time of data
in the B-radix system. For example, the Gtime(4)=50%,
Gtime(8)= 33.33%, Gtime(16)=25%,
Gtime(1024)=10%. This data shows that there is not much
of gain as we increase the radix and shows no linear enhancement at all.
the aforementioned cases, we will define a function that measures the
z system performance relative to the B system performance on a scale
of zero to 100% and call it the Performance-function.
The higher the performance the better the system is. We will define the
performance function as Per(Z)=m
is a normalization factor. From the performance function, we see that as we
increase z the multiplexing-time decreases and the pins-cut increases and as we
decrease z, the multiplexing-time increases and the pins-cut decreases.
This ensures that for any increased value of z, there is a reduction in the
multiplexing-time and an increase in pins-cut, which what we desire.
Since the performance function measures the z system performance relative to the B system performance, then it must satisfy the following two conditions. (1) The performance must be zero when Z=B because the new system radix is just equal to the old system radix to be optimized and we have no performance is gained at all. (2) The performance must be zero when z approaches infinity because at infinity we move from a discrete system (digital) to a continuous system (analog). If we check the performance function, we find out that it satisfies these two conditions: (1) Per(B)= m [Ln(B)/Ln(B)] [1-(Ln(B)/Ln(B))]= m(1x0)=0; (2) PER(µ)= m(0x1)=0.
The optimum radix is equal to the square of the system radix to be
optimized. One of the important aspects to note about this result is
that the conversions between the two systems are direct conversions that make
the interface units between the two systems fast and simple especially when a
mixed radix system is considered. Also, it does not specify an absolute optimum
system and gives the optimum system relative to a given system. For example, the
optimum system for the binary system is the quaternary system, for the ternary
system is the radix-9 system and for the quaternary system is the hexadecimal
system and so on. This result agrees with the analysis of George Abraham in 
p.395 in his statement For example, if n is the number of binary devices
or circuits which can be integrated monolithically to form new devices which
operate at radices higher than the binary (meaning optimum radix=3), then
radices higher than the ternary can be more efficient both from the standpoint
of storage density as well as component-wise than either the binary or ternary.
in  showed that the optimum radix is equal to e=2.718 suggesting that
three-valued systems are the most economical. Out result is different from his
result because he did not consider the multiplexing-time factor in his analysis and assumed
that circuit complexity is linearly proportional to the system radix. According
to George Abraham in  this assumption has to be verified and he stated in 
The validity of the assumption that the equipment complexity is
proportional to the product of n and R must be investigated for each
configuration under consideration. Also, according to Butler in ,
practical cases do not support the linearity assumption and he stated in  p.v
... although practice would suggest something less than a linear
relationship. In this case, a larger number of logic levels is optimum.
Also, Allen and Givone in  showed that the optimum system is strictly greater
than not equal to e=2.71. Thus, the optimum result a agrees with the analysis of
George, Butler and Allen.
In this paper we have shown how the optimum system was found based on the pinout-problem and multiplexing-time problem. We also have shown (1) that the optimum system, relative to a given system, is given by Zoptimum=B²; (2) that the optimum system which will optimize the properties of the binary system is the quaternary system.
S.L. Hurst, Multiple-Valued
Logic-Its Status and its Future, IEEE trans. computers, Vol.
C-33, No 12, pp.1160-1179, DEC 1984.
J. T. Butler, Multiple-Valued
Logic in VLSI Design, IEEE Computer Society Press Technology
C.M. Allen, D.D. Givone
The Allen-Givone Implementation Oriented Algebra, in Computer
Science and Multiple-Valued Logic: Theory and Applications, D.C. Rine,
second edition, D.C. Rine, ed., The Elsevier North-Holland, New York, N.Y.,
1984. pp. 268-288.
G. Abraham, Multiple-Valued
Negative Resistance Integrated Circuits, in Computer Science and
Multiple-Valued Logic: Theory and Applications, D.C. Rine, second edition,
D.C. Rine, ed., The Elsevier North-Holland, New York, N.Y., 1984. pp. 394-446.
J. L. Baer, Computer
System Architecture, New York: Computer Science Press, 1989.